Solid State Drives Architecture
Solid state drives represent a fairly new technology in the storage market. Flash drives (like USB thumb drives, memory cards in camcorders and cameras) have been used for years, but this technology has grown to the point where it rivals the traditional hard disk drives (HDDs) using the same form factor. At first glance, there are a few advantages to solid state drives compared to traditional hard disk drives: no moving parts, less power consumption, faster access times and silent operation. It is no wonder that the manufacturers' marketing departments have been drawing the public's attention to these advantages.
Most SSDs use multi-channel flash microcontrollers
and advanced controller technologies to extend the reliability and speed. The architecture inside a high performance SSD is more complicated than that in most RAID systems. Individual non-volatile NAND flash memory chips that form an SSD
are relatively slow. The performance is scaled when the number of them is used in parallel inside an SSD. It allows increasing the bandwidth and effectively hiding the high latencies of the individual NAND flash chips. To make the drives even faster, such techniques as data striping (like in RAIDs) and interleaving are implemented.
Flash memory stores data in individual memory cells. There are two types of NAND flash memory - single-level cell (SLC) and multi-level cell (MLC). The
memory uses a single level per cell so each cell holds 1 bit of data as opposed to the
memory which uses multiple levels per cell currently allowing to store 2 bits. The MLC memory is cheaper since it has more density, but it also results in the possibility of more errors and less write/erase cycles. Errors that appear during normal device operation can be detected and corrected by the controller using error correction code or ECC.
NAND is storing three bits per cell, used primarily in consumer products, like USB thumb drives, client SSDs, and other portable media devices, that don't require top performance and endurance.
Further on TLC NAND, ACE began working on a solution after many consumers contacted the company when they could not read their data from locked-down TLC based Samsung 840 EVOs. A drop in read performance of old data is common for all SSDs, but the problem can accelerate in this particular SSD, causing firmware to lock down the drive while it’s still fairly fresh.
This article documents the Samsung 840 EVO SSD's performance problems and includes links to the two firmware updates Samsung issued to attempt to fix the problem before abandoning the TLC NAND memory that was at the center of the problem: Samsung Releases Second 840 EVO Performance Fix
NAND memory is accessed by blocks. Each block consists of a number of pages (typically 512, 2048, or 4096 bytes in size). Blocks available to high level software on a logical level are mapped to physical blocks by the controller. Any block needs to be erased before it can be written to. As a result, the device's durability factor is measured in write/erase cycles. To ensure that no single block prematurely fails due to a high number of write/erase cycles, SSDs employ a technique called "wear leveling
". Wear leveling dynamically maps logical blocks to physical blocks in such a way as to ensure that write/erase cycles are evenly distributed across all available blocks.
The management algorithms and techniques such as advanced error correcting, wear leveling, and bad block management maximize the drive's operating life and extends
, but it complicates the design. The algorithms which map logical addresses to physical media locations vary from manufacturer to manufacturer, and the details are closely guarded commercial secrets. All these technologies used in SSDs to extend the reliability at the same time complicate the data recovery process immensely in the case of a failure.
Data Recovery's R&D team has developed an advanced solid storage drive recovery process of rebuilding multiple sets of NAND flash memory dumps. The process consists of reading individual NAND flash memory chips into raw images, then applying reverse-engineered ECC and special mapping algorithms to unscramble each image and assembling the numerous unscrambled sets into a single full drive image. The resulting image then can be processed using normal data recovery methods.